.\" $Id: PAPI_presets.3,v 1.8 2004/09/29 16:24:14 terpstra Exp $
.TH PAPI_presets 3 "September, 2004" "PAPI Programmer's Reference" "PAPI"

.SH NAME
PAPI_presets \- PAPI predefined named events

.SH SYNOPSIS
.nf
.B #include <papi.h>
.fi

.SH DESCRIPTION
The PAPI library names a number of predefined, or preset events. This set
is a collection of events typically found in many
CPUs that provide performance counters. A PAPI preset event name is
mapped onto one or more of the countable native events on each hardware platform.
On any particular platform, the preset can either be directly available 
as a single counter, derived using a combination of counters or unavailable.
.LP
The PAPI preset events can be broken loosely into several categories, 
as shown in the table below:

.B PAPI Preset Event Definitions by Category: 
.TS H
allbox, tab($);
cB cB
cI s
lB lw(45).
.TH
Name$Description
Conditional Branching
PAPI_BR_CN$T{
Conditional branch instructions 
T}
_
PAPI_BR_INS$T{
Branch instructions 
T}
_
PAPI_BR_MSP$T{
Conditional branch instructions mispredicted 
T}
_
PAPI_BR_NTK$T{
Conditional branch instructions not taken 
T}
_
PAPI_BR_PRC$T{
Conditional branch instructions correctly predicted 
T}
_
PAPI_BR_TKN$T{
Conditional branch instructions taken 
T}
_
PAPI_BR_UCN$T{
Unconditional branch instructions 
T}
_
PAPI_BRU_IDL$T{
Cycles branch units are idle 
T}
_
PAPI_BTAC_M$T{
Branch target address cache misses 
T}
.T&
cI s
lB lw(45).
Cache Requests: 
PAPI_CA_CLN$T{
Requests for exclusive access to clean cache line 
T}
_
PAPI_CA_INV$T{
Requests for cache line invalidation 
T}
_
PAPI_CA_ITV$T{
Requests for cache line intervention 
T}
_
PAPI_CA_SHR$T{
Requests for exclusive access to shared cache line 
T}
_
PAPI_CA_SNP$T{
Requests for a snoop 
T}
.T&
cI s
lB lw(45).
Conditional Store: 
PAPI_CSR_FAL$T{
Failed store conditional instructions 
T}
_
PAPI_CSR_SUC$T{
Successful store conditional instructions 
T}
_
PAPI_CSR_TOT$T{
Total store conditional instructions 
T}
.T&
cI s
lB lw(45).
Floating Point Operations: 
PAPI_FAD_INS$T{
Floating point add instructions 
T}
_
PAPI_FDV_INS$T{
Floating point divide instructions 
T}
_
PAPI_FMA_INS$T{
FMA instructions completed 
T}
_
PAPI_FML_INS$T{
Floating point multiply instructions 
T}
_
PAPI_FNV_INS$T{
Floating point inverse instructions 
T}
_
PAPI_FP_INS$T{
Floating point instructions 
T}
_
PAPI_FP_OPS$T{
Floating point operations 
T}
_
PAPI_FP_STAL$T{
Cycles the FP unit 
T}
_
PAPI_FPU_IDL$T{
Cycles floating point units are idle 
T}
_
PAPI_FSQ_INS$T{
Floating point square root instructions 
T}
.T&
cI s
lB lw(45).
Instruction Counting: 
PAPI_FUL_CCY$T{
Cycles with maximum instructions completed 
T}
_
PAPI_FUL_ICY$T{
Cycles with maximum instruction issue 
T}
_
PAPI_FXU_IDL$T{
Cycles integer units are idle 
T}
_
PAPI_HW_INT$T{
Hardware interrupts 
T}
_
PAPI_INT_INS$T{
Integer instructions 
T}
_
PAPI_TOT_CYC$T{
Total cycles 
T}
_
PAPI_TOT_IIS$T{
Instructions issued 
T}
_
PAPI_TOT_INS$T{
Instructions completed 
T}
_
PAPI_VEC_INS$T{
Vector/SIMD instructions 
T}
.T&
cI s
lB lw(45).
Cache Access: 
PAPI_L1_DCA$T{
L1 data cache accesses 
T}
_
PAPI_L1_DCH$T{
L1 data cache hits 
T}
_
PAPI_L1_DCM$T{
L1 data cache misses 
T}
_
PAPI_L1_DCR$T{
L1 data cache reads 
T}
_
PAPI_L1_DCW$T{
L1 data cache writes 
T}
_
PAPI_L1_ICA$T{
L1 instruction cache accesses 
T}
_
PAPI_L1_ICH$T{
L1 instruction cache hits 
T}
_
PAPI_L1_ICM$T{
L1 instruction cache misses 
T}
_
PAPI_L1_ICR$T{
L1 instruction cache reads 
T}
_
PAPI_L1_ICW$T{
L1 instruction cache writes 
T}
_
PAPI_L1_LDM$T{
L1 load misses 
T}
_
PAPI_L1_STM$T{
L1 store misses 
T}
_
PAPI_L1_TCA$T{
L1 total cache accesses 
T}
_
PAPI_L1_TCH$T{
L1 total cache hits 
T}
_
PAPI_L1_TCM$T{
L1 total cache misses 
T}
_
PAPI_L1_TCR$T{
L1 total cache reads 
T}
_
PAPI_L1_TCW$T{
L1 total cache writes 
T}
_
PAPI_L2_DCA$T{
L2 data cache accesses 
T}
_
PAPI_L2_DCH$T{
L2 data cache hits 
T}
_
PAPI_L2_DCM$T{
L2 data cache misses 
T}
_
PAPI_L2_DCR$T{
L2 data cache reads 
T}
_
PAPI_L2_DCW$T{
L2 data cache writes 
T}
_
PAPI_L2_ICA$T{
L2 instruction cache accesses 
T}
_
PAPI_L2_ICH$T{
L2 instruction cache hits 
T}
_
PAPI_L2_ICM$T{
L2 instruction cache misses 
T}
_
PAPI_L2_ICR$T{
L2 instruction cache reads 
T}
_
PAPI_L2_ICW$T{
L2 instruction cache writes 
T}
_
PAPI_L2_LDM$T{
L2 load misses 
T}
_
PAPI_L2_STM$T{
L2 store misses 
T}
_
PAPI_L2_TCA$T{
L2 total cache accesses 
T}
_
PAPI_L2_TCH$T{
L2 total cache hits 
T}
_
PAPI_L2_TCM$T{
L2 total cache misses 
T}
_
PAPI_L2_TCR$T{
L2 total cache reads 
T}
_
PAPI_L2_TCW$T{
L2 total cache writes 
T}
_
PAPI_L3_DCA$T{
L3 data cache accesses 
T}
_
PAPI_L3_DCH$T{
L3 Data Cache Hits 
T}
_
PAPI_L3_DCM$T{
L3 data cache misses 
T}
_
PAPI_L3_DCR$T{
L3 data cache reads 
T}
_
PAPI_L3_DCW$T{
L3 data cache writes 
T}
_
PAPI_L3_ICA$T{
L3 instruction cache accesses 
T}
_
PAPI_L3_ICH$T{
L3 instruction cache hits 
T}
_
PAPI_L3_ICM$T{
L3 instruction cache misses 
T}
_
PAPI_L3_ICR$T{
L3 instruction cache reads 
T}
_
PAPI_L3_ICW$T{
L3 instruction cache writes 
T}
_
PAPI_L3_LDM$T{
L3 load misses 
T}
_
PAPI_L3_STM$T{
L3 store misses 
T}
_
PAPI_L3_TCA$T{
L3 total cache accesses 
T}
_
PAPI_L3_TCH$T{
L3 total cache hits 
T}
_
PAPI_L3_TCM$T{
L3 cache misses 
T}
_
PAPI_L3_TCR$T{
L3 total cache reads 
T}
_
PAPI_L3_TCW$T{
L3 total cache writes 
T}
.T&
cI s
lB lw(45).
Data Access: 
PAPI_LD_INS$T{
Load instructions 
T}
_
PAPI_LST_INS$T{
Load/store instructions completed 
T}
_
PAPI_LSU_IDL$T{
Cycles load/store units are idle 
T}
_
PAPI_MEM_RCY$T{
Cycles Stalled Waiting for memory Reads 
T}
_
PAPI_MEM_SCY$T{
Cycles Stalled Waiting for memory accesses 
T}
_
PAPI_MEM_WCY$T{
Cycles Stalled Waiting for memory writes 
T}
_
PAPI_PRF_DM$T{
Data prefetch cache misses 
T}
_
PAPI_RES_STL$T{
Cycles stalled on any resource 
T}
_
PAPI_SR_INS$T{
Store instructions 
T}
_
PAPI_STL_CCY$T{
Cycles with no instructions completed 
T}
_
PAPI_STL_ICY$T{
Cycles with no instruction issue 
T}
_
PAPI_SYC_INS$T{
Synchronization instructions completed 
T}
.T&
cI s
lB lw(45).
TLB Operations: 
PAPI_TLB_DM$T{
Data translation lookaside buffer misses 
T}
_
PAPI_TLB_IM$T{
Instruction translation lookaside buffer misses 
T}
_
PAPI_TLB_SD$T{
Translation lookaside buffer shootdowns 
T}
_
PAPI_TLB_TL$T{
Total translation lookaside buffer misses 
T}
.TE
.LP

.SH AUTHORS
Nils Smeds <smeds@cs.utk.edu>

.SH BUGS
The exact semantics of an event counter are platform dependent.  PAPI
preset names are mapped onto available events in a way so as to
count as similar types of events as possible on different
platforms. Due to hardware implementation differences it is not
necessarily possible to directly compare the counts of a particular
PAPI event obtained on different hardware platforms.

.SH SEE ALSO
.BR PAPI "(3), " PAPI_native "(3), " PAPI_enum_event "(3), " PAPI_get_event_info "(3), "
.BR PAPI_event_code_to_name "(3), " PAPI_event_name_to_code "(3)"
